Serial data receiver with decision feedback equalizer with feed forward technique

ABSTRACT

A serial data receiver is disclosed. In one embodiment, a receiver includes an amplifier circuit configured to receive one or more signals that encode a serial data stream that includes a plurality of data symbols and to perform a comparison of the one or more signals to a threshold value to generate a recovered data symbol. The receiver circuit further includes a threshold circuit configured to generate a delayed version of the one or more signals. The threshold circuit is further configured to generate a delayed data symbol using the delayed version of the one or more signals and adjust the threshold value using the delayed data symbol.

BACKGROUND Technical Field

This disclosure is directed to communications systems, and moreparticularly, to receiver circuits in communications systems.

Description of the Related Art

High-speed communications systems are increasingly common in variousdevices. Such systems transmit data at high speeds across acommunications link. Many such systems transmit data serially, althoughhigh-speed parallel communications system are used in many applications.

To ensure data is transferred correctly and without errors, varioustechniques are used. For example, decision feedback equalization is usedto reduce distortion produced by inter-symbol interference (ISI) byevaluating a currently received symbol based on one or more previouslyreceived symbols. Many other techniques are utilized as well.

SUMMARY

A serial data receiver is disclosed. In one embodiment, a receiverincludes an amplifier circuit configured to receive one or more signalsthat encode a serial data stream that includes a plurality of datasymbols and to perform a comparison of the one or more signals to athreshold value to generate a recovered data symbol. The receivercircuit further includes a threshold circuit configured to generate adelayed version of the one or more signals. The threshold circuit isfurther configured to generate a delayed data symbol using the delayedversion of the one or more signals and adjust the threshold value usingthe delayed data symbol.

In one particular (non-limiting) embodiment, the threshold circuiteffectively acts as a decision feedback equalization (DFE) circuit thatimplements DFE using a feed forward technique. For example, anembodiment of a threshold circuit may be implemented using a Schmitttrigger circuit and a logic circuit. The Schmitt trigger and theamplifier may concurrently receive an incoming signal having a pluralityof symbols therein. While the amplifier processes the incoming signal,the Schmitt trigger may generates a delayed version (or delayedcomplement) of the incoming signal. A logic circuit coupled to theoutput of the Schmitt trigger may receive the delayed version of theincoming signal and generate a threshold adjustment signal. The logiccircuit may then adjust the threshold of the amplifier. Using theadjusted threshold, the amplifier may evaluate the next incoming symbolbased on the value of previous symbol.

BRIEF DESCRIPTION OF THE DRAWINGS

The following detailed description makes reference to the accompanyingdrawings, which are now briefly described.

FIG. 1 is a diagram of one embodiment of a receiver.

FIG. 2 is a diagram of another embodiment of a receiver.

FIG. 3 is a schematic diagram of one embodiment of a receiver.

FIG. 4 is a timing diagram of the operation of one embodiment of areceiver.

FIG. 5 is a flow diagram illustrating an embodiment of a method foroperating a receiver.

FIG. 6 is a flow diagram illustrating another embodiment of a method foroperating a receiver.

FIG. 7 is block diagram illustrating one embodiment of a communicationssystem.

FIG. 8 is a block diagram illustrating embodiments of an example system.

DETAILED DESCRIPTION OF EMBODIMENTS

Many digital communications systems use decision feedback equalization(DFE) in receivers to compensate for distortion caused by inter-symbolinterference (ISI). Thus, many receivers use DFE circuits that utilizethe history of previously received symbols to evaluate a currentlyreceived symbol.

In prior art DFE circuits, certain conditions can occur that cause theoutput to oscillate. In particular, if the input rise/fall time isgreater than the period of oscillation or if the input voltage is heldbetween 0 and the supply voltage for a sufficient amount of time. To putit another way, oscillation occurs if the feedback signal reaches theinput to change the trip point/threshold before the output has fullysettled. One solution to the problem could be to add a delay to thefeedback path. However, controlling the delay requires more powerconsumption.

The present disclosure makes use of the insight that if the shifting ofthe threshold could be delay to allow the output to fully settle, theoscillation could be eliminated. Accordingly, the present disclosurecontemplates a receiver circuit having a feedforward path that delaysthe shifting of the threshold. Instead of the traditional feedback toimplement DFE, a feed-forward path having a hysteresis circuit (e.g., aSchmitt trigger) between the input pad and the inverter is implemented.The hysteresis circuit, using the history of the most recently receivedsymbol, delays the changing of the threshold for the next symbol untilafter the output has been provided enough time to settle. The use of thehysteresis circuit allows implementation of DFE without actuallyproviding a feedback loop from the output. Instead, the history of theprevious symbol is effectively captured by the hysteresis circuit toimplement the feedback function. This results in a receiver circuit thatcan effectively implement DFE while eliminating the oscillationdescribed above. The receiver circuit may also consume less power incomparison with circuits that delay feedback from the output.Furthermore, the eye for received signals may be greater as wellrelative to receivers that utilize traditional feedback in implementingDFE.

The present disclosure is now discussed in further detail, beginningwith embodiments of a receiver circuit. A schematic diagram of anembodiment of a receiver circuit is then discussed, followed by a timingdiagram of its operation. Methods for operating a receiver circuit inaccordance with the disclosure are then discussed. An examplecommunications system is then described, followed by that of examplesystems in which it may be implemented.

Receiver Circuit with DFE Implemented Using Feed Forward Technique:

Turning now to FIG. 1 , a block diagram of one embodiment of a receiveris shown. In the embodiment shown, receiver 100 includes an amplifiercircuit 103 and a threshold circuit 105. Amplifier 103 in the embodimentshown is configured to receive signals that encode a serial data streamthat includes a plurality of data symbols. The values of these symbolsare determined using an adjustable threshold value. The one or moresignals are compared to the threshold value in order to generaterecovered data symbols. The threshold used by amplifier 103 at anyparticular time is determined by threshold circuit 105.

Threshold circuit 105 in the embodiment shown is coupled to receive thesignals containing data symbols concurrently with amplifier 103, and isconfigured to generate a delayed version of the received signals, usingdelay circuit 106. Using the received signals, threshold circuit 105generates a delayed data symbols. Using the delayed data symbols,threshold circuit 105 in the embodiment shown adjusts the thresholdvalue used as a basis of comparison by amplifier 103. In this manner,receiver 100 implements DFE using a feed-forward technique that delaysthe data symbols such that the threshold used by amplifier 103 forevaluating a particular symbol is based on the history of at least oneprevious symbol.

Delay circuit 106 in the embodiment shown may be one of a number ofdifferent types of circuits. Generally speaking, delay circuit 105 mayuse some form of hysteresis to generate a lockout period that holds thethreshold at a particular value while amplifier 103 evaluates a signalto recover a data symbol. This in turn may prevent oscillation that mayoccur in previous receivers in which the feedback signal causes a changeof the threshold before the amplifier has fully settled. Generating alockout period using the delay circuit 106 thus allows time for theoutput signal to settle, without oscillation, and thus provide anaccurately recovered data symbol.

FIG. 2 is a block diagram of another embodiment of a receiver circuit.More particularly, receiver 200 is a more detailed version of anembodiment of receiver 100 as shown in FIG. 1 , although it is to beunderstood that the embodiment of FIG. 2 is not intended to be limiting.

In the embodiment shown in FIG. 2 , an input signal may be received viapad 211, with recovered data symbols being provided via a level shifter213 coupled to the output node, Out. Amplifier 203 in the embodimentshown may be similarly configured to that shown in FIG. 1 , and maycompare incoming signals to an adjustable threshold to recover andprovide output data symbols.

Threshold circuit 205 in the embodiment shown includes a Schmitt trigger209 and a DFE logic circuit 207. Schmitt trigger 209 in the embodimentshown provides, through history, delay for threshold circuit 205. One ofa number of different types of circuits may be used to implement Schmitttrigger 209. In one embodiment, Schmitt trigger 209 may be implementedas a classic MOSFET Schmitt trigger circuit. Embodiments in whichSchmitt trigger 209 is implemented using bipolar transistors or variousnon-inverting amplifier configurations are also possible andcontemplated. Generally speaking, Schmitt trigger 209 may be implementedin any suitable circuit configuration to achieve the desired operationof threshold circuit 209.

The output of Schmitt trigger 209 is provided to DFE logic circuit 207.In the embodiment shown, DFE logic circuit 207 is configured to for acurrently received symbol, select the next threshold value for amplifier103 based on the delayed data symbol received from Schmitt trigger 209and an N-bit input code, Vref_DFE[N−1:0] received from control register217. The input code may be any integer number of bits, N, and may dependon the particular arrangement of DFE logic circuit 207.

In some embodiments, the input code may be a static code that is inputinto control register 217 at, e.g., startup time, manufacture time, orany other suitable time. In other embodiments, control register 217 maybe a dynamic code that may be updated from time to time during operationof receiver 200. In this particular embodiment, a calibration circuit223 is coupled to control register 217 and is configured to provide theinput code thereto based on a calibration operation. Calibration circuit223 may also be coupled to other circuits and may be configured to carryout various functions that cause a calibration to be performed. Suchcalibrations may include receiver 200 receiving input signals andevaluating the recovered symbols vs. some expected value. Calibrationsmay be performed on a periodic basis and/or at other times, such asduring a change of a performance state (supply voltage and/or clockfrequency) of the system in which receiver 200 is implemented.

The output of DFE logic circuit 207 in the embodiment shown may be oneor more signals that control the threshold value that amplifier 203 usesto evaluate incoming signals in order to recover symbols therefrom. Thethreshold at any given time in the embodiment shown is dependent on atleast one previously received symbol. For example, in a binary system,if the previous symbol occurred as a result of a low-to-high transition,the threshold may be set to a first value that is greater than themidpoint between a reference voltage and a supply voltage provided tothe amplifier. Thus, for a high-to-low transition that occurs subsequentto the low-to-high transition, the output of amplifier 203 will switchresponsive to the signal voltage falling below the first threshold. Ifthe previous symbol occurred as a result of a high-to-low transition,the threshold value may be set by DFE logic circuit 207 to a secondvalue that is less than the first value and lower than the midpointbetween the reference voltage and the supply voltage. Thus, for asubsequent low-to-high transition, the output of amplifier 203 willswitch as soon as the signal voltage crosses the second threshold.

In some embodiments, the signal voltages may be different than thesupply voltage of circuits downstream from receiver 200. Accordingly,the embodiment shown in FIG. 2 includes a level shifter 213, which isconfigured to level-shift the output signal from amplifier 203 to thevoltage domain of the downstream circuits.

FIG. 3 is a schematic diagram of one embodiment of a receiver. In theembodiment shown, receiver 300 includes a Schmitt trigger 309, anamplifier 303, and a level shifter 313. A DFE logic circuit is alsoimplemented using logic gates NAND1, NAND2, NOR1, NOR2 and NOR3. Theselogic gates are each coupled to receive an input code, which is two bitsin this particular embodiment, although other embodiments arranged fordifferent sized codes are possible and contemplated.

The input code in this embodiment comprises Vref_DFE[1:0]. These bit areinput into NOR1, and if at least one of them is a logic 1, the outputDFE_enb is low, while inverter I1 generates DFE_en as a logic high.These signals, DFE_en as a logic high and DFE_enb as a logic low,operate as DFE enable signals to enable Schmitt trigger 309 to carry outits functions in performing DFE for receiver 300. When DFE_en is low andDFE_enb is high, and thus Schmitt trigger 309 is not enabled, signalsmay pass through receiver 300 with no DFE performed thereon.Additionally, when DFE is not enabled, N35 is activated to pull node ST1low.

Schmitt trigger 309 includes a pull-up stack comprising transistors P31,P32, and P33, and a pull-down stack comprising transistors N31, N32, andN33. Of these devices, P32 and P33 in the pull-up stack and N31 and N32in the pull-down stack have respective gate terminals coupled to receivethe input signal. Transistor N33 is coupled to receive the DFE_en signalon its respective gate terminal, while transistor P31 is coupled toreceive the DFE_enb signal on its respective gate terminal. The pull-upand pull-down stacks, when enabled, operate to perform a stronginversion of the input signal on the ST1 node.

When node ST1 is pulled low by the pull-down stack, P34 is activated.Since N35 is active due to the high on DFE_en, a pull-down path isprovided between the drain terminal of P32 and ground. When ST1 ispulled high by the pull-up stack, N34 is activated, thereby generating apull-up path between the drain terminal of N32 and the supply voltagenode VDD.

Schmitt trigger 309 also includes an inverter comprising N356 and P37,which inverts the signal on ST1 to produce the complementary value onnode ST2. The value of ST2 is provided as an input to logic gates NAND1,NAND2, NOR2, and NOR3. Logic gate NAND1 is coupled to receiveVref_DFE[1] as a second input, while the complementary value VrefDFEb[1] is provided as the second input to NOR3. Logic gate NAND2 iscoupled to receive Vref_DFE[0] as its second input, while its complementVref DFEb[0] is provided as the second input to NOR2. Due to thearrangement of Schmitt trigger 309 relative to amplifier 303, the logicvalue of ST2 may correspond to a previously recovered symbol relative tothe value that is received on the input of amplifier 303.

Amplifier 303 in the embodiment shown includes three pull-up stacks, thefirst comprising P37 and P38, the second comprising P39 and P40, and thethird comprising P41 and P42. Amplifier 303 further includes threepull-down stacks, the first comprising N37 and N38, the secondcomprising N39 and N40, and the third comprising N41 and N42. The firstpull-up stack and the first pull-down stack are arranged such that theymay be activated irrespective of whether DFE is enabled at a particulartime. The other pull-up and pull-down stacks may be enabled depending onthe states of the output signals of NAND1, NAND2, NOR2 and NOR3. WhenDFE is enabled, the output signals of the logic gates, which are basedon the input code and the current state of ST2, is based on a previouslyreceived symbol. These output values enable or disable correspondinglycoupled pull-up/pull-down stacks, and thus set the threshold foramplifier 303 to evaluate a signal currently received on its input, andthus recover a symbol therefrom. Depending on the input codeVref_DFE[1:0], anywhere from one to three of the pull-up/pull-downstacks may be active at a given time, thereby setting a threshold value.The Amp_Out node is thus based on the voltage of the input signal andthe threshold set per the operation described above. The Amp_Out signalis then provided to level shifter 313, which in turn provide thelevel-shifted output signal, Out.

Timing Diagram:

FIG. 4 is a timing diagram illustrating the operation of one embodimentof a receiver in accordance with this disclosure. The operationillustrated by FIG. 4 may be carried out by any of the receiverembodiments discussed above.

In the illustrated example, the input signal makes an initial transitionfrom low to high (VDD). The threshold at this time is set for thelow-to-high transition, and is less than 0.5*VDD. When the input signalcrosses this value, the receiver output, Rx Out, transitions from low tohigh. Due to hysteresis, the Schmitt trigger output is delayed intransitioning, but eventually falls low at some point after Rx Outtransitions high. This delay between the time the input signal crossesthe low-to-high threshold and the high-to-low transition of SchmittTrigger Out allows sufficient time for settling of Rx Out and thusprevents oscillation that can occur in previous receivers using DFE.Furthermore, when Schmitt Trigger Out falls low, the switching thresholdfor the amplifier is adjusted to the High-to-Low threshold, which isgreater than 0.5*VDD. At a subsequent time, when the input signal fallslow, Rx Out falls low as the input signal crosses the High-to-Lowthreshold. The Schmitt Trigger Out signal transitions from low to highat a delay/hysteresis time thereafter. In the delay time between theinput signal falling below the High-to-Low threshold and thetransitioning from low to high of Schmitt Trigger Out, the amplifier isprovided sufficient time to allow Rx Out to settle without oscillation.

Methods for Operating a Communications Subsystem

FIG. 5 is a flow diagram of one embodiment of a method for operating acommunications system. Method 500 as illustrated in FIG. 5 may becarried out by any of the receivers discussed herein. Embodiments of areceiver that is capable of carrying out Method 500, but not explicitlydisclosed herein, is also considered to fall within the scope of thisdisclosure.

Method 500 includes receiving, by an amplifier circuit, one or moresignals that encode a serial data stream that includes a plurality ofdata symbols (block 505). The method further includes performing, usingthe amplifier circuit, a comparison of the one or more signals to athreshold value to generate a recovered data symbol (block 510).Concurrent with the above, Method 500 includes generating, using athreshold circuit, a delayed version of the one or more signals (block515), and generating, using the threshold circuit, a delayed data symbolusing the delayed version of the one or more signals (block 520).Thereafter, Method 500 includes adjusting, using the threshold circuit,the threshold value using the delayed data symbol.

The threshold circuit includes, in various embodiment, a delay circuitand a logic circuit. In a receiver configured as such, the methodfurther includes producing the delayed data symbol, using the delaycircuit, wherein producing the delayed data symbol includes the delaycircuit providing hysteresis to the one or more signal and selecting athreshold value for a currently received data symbol using the logiccircuit based on the delayed data symbol and an input code. The inputcode may be stored in a register, and thus embodiments of method mayfurther include providing the input code, from a register, to the logiccircuit. In some embodiments, the input code is a static code that isset at, e.g., startup time or more generally, sometime prior to normaloperations. The method may further include performing a calibration toupdate the input code, which may be carried out on a periodic basis.

Embodiments of the method may further include the threshold circuitchanging the threshold level from a first level to a second level at afirst delay time subsequent to a transition of a recovered data symbolfrom a first logic value to a second logic value. Such embodiments ofthe method further include the threshold circuit changing the thresholdlevel from the second level to the first level at a second delay timesubsequent to a transition of the recovered data symbol from the secondlogic value to the first logic value.

FIG. 6 is a flow diagram of another embodiment of a method for operatinga receiver. Method 600 may be carried out by embodiments of a receiversuch as those shown in FIGS. 2 and 3 . Receiver embodiments notexplicitly disclosed herein that are nevertheless capable of carryingout Method 600 are also considered to fall within the scope of thisdisclosure.

Method 600 begins with providing a low-to-high (e.g., logic 0 tologic 1) symbol transition to an amplifier and a Schmitt trigger of areceiver circuit (block 605). The method further includes the amplifierswitching the state of the amplifier output signal, in response to thelow-to-high transition, based on a first threshold that is set by athreshold circuit that includes the Schmitt trigger (block 610). Afterreceiving the low-to-high transition, the Schmitt trigger causes thethreshold circuit to switch the threshold of the amplifier from thefirst threshold to a second threshold (block 615). The switching fromthe first threshold to the second threshold occurs after the amplifierhas already responded to the low-to-high symbol transition.

At some point following the changing of the threshold, a high-to-lowsymbol transition occurs and is provided to the amplifier and theSchmitt trigger (block 620). In response to receiving the high-to-lowsymbol transition, the amplifier switches its output based on the secondthreshold (block 625). At some time thereafter, based on the output ofthe Schmitt trigger, the threshold circuit cause the amplifier thresholdto change from the second threshold to the first threshold.

Communications System:

FIG. 7 is a block diagram of one embodiment of a communications systemthat may utilize a receiver as disclosed herein. In the embodimentshown, system 700 includes a transmitter 705 and a receiver 710. Thereceiver may implement DFE using the various techniques describedherein, such as those described with reference to FIGS. 1-4 . It isnoted that, while the system illustrated here is unidirectional,bi-directional systems are also possible and contemplated, with atransmitter and a receiver on each side of the link 708.

The system as shown in FIG. 7 may be one of a number of different types.For example, system 700 may implement a link between a memory controllerand a memory in one embodiment. Embodiments of various point-to-pointcommunications systems between, e.g., a system-on-a-chip (SoC) and aperipheral device are also possible and contemplated. Intra-chipcommunications links are also possible and contemplated within the scopeof this disclosure. In general, communication system 700 may be any typeof system that implements DFE at a receiver in the manner describedabove.

Example System:

Turning next to FIG. 8 , a block diagram of one embodiment of a system800 is shown that may incorporate and/or otherwise utilize the methodsand mechanisms described herein. In the illustrated embodiment, thesystem 800 includes at least one instance of a system on chip (SoC) 806which may include multiple types of processing units, such as a centralprocessing unit (CPU), a graphics processing unit (GPU), or otherwise, acommunication fabric, and interfaces to memories and input/outputdevices. In some embodiments, one or more processors in SoC 806 includesmultiple execution lanes and an instruction issue queue. In variousembodiments, SoC 806 is coupled to external memory 802, peripherals 804,and power supply 808.

A power supply 808 is also provided which supplies the supply voltagesto SoC 806 as well as one or more supply voltages to the memory 802and/or the peripherals 804. In various embodiments, power supply 808represents a battery (e.g., a rechargeable battery in a smart phone,laptop or tablet computer, or other device). In some embodiments, morethan one instance of SoC 806 is included (and more than one externalmemory 802 is included as well).

The memory 802 is any type of memory, such as dynamic random accessmemory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2,DDR3, etc.) SDRAM (including mobile versions of the SDRAMs such asmDDR3, etc., and/or low power versions of the SDRAMs such as LPDDR2,etc.), RAMBUS DRAM (RDRAM), static RAM (SRAM), etc. One or more memorydevices are coupled onto a circuit board to form memory modules such assingle inline memory modules (SIMMs), dual inline memory modules(DIMMs), etc. Alternatively, the devices are mounted with a SoC or anintegrated circuit in a chip-on-chip configuration, a package-on-packageconfiguration, or a multi-chip module configuration.

SoC 806 in the embodiment shown, as well as various ones of the otherdevices shown in FIG. 8 , may include components of a communicationssystem having a receiver as discussed above. In some embodiments, two ofthe components shown in FIG. 8 may be arranged to communicate with eachother over a link that includes, at one end if not both, a receiver inaccordance with the disclosure herein. Such a receiver may include DFEcircuitry as disclosed herein to, e.g., adjust thresholds forinterpreting incoming symbols. The DFE circuitry may utilize a thresholdcircuit in a feed forward configuration as shown in, e.g., any of FIGS.1-3 , or any other embodiment that falls within the scope of thisdisclosure.

The peripherals 804 include any desired circuitry, depending on the typeof system 800. For example, in one embodiment, peripherals 804 includesdevices for various types of wireless communication, such as Wi-Fi,Bluetooth, cellular, global positioning system, etc. In someembodiments, the peripherals 804 also include additional storage,including RAM storage, solid state storage, or disk storage. Theperipherals 804 include user interface devices such as a display screen,including touch display screens or multitouch display screens, keyboardor other input devices, microphones, speakers, etc.

As illustrated, system 800 is shown to have application in a wide rangeof areas. For example, system 800 may be utilized as part of the chips,circuitry, components, etc., of a desktop computer 810, laptop computer820, tablet computer 830, cellular or mobile phone 840, or television850 (or set-top box coupled to a television). Also illustrated is asmartwatch and health monitoring device 860. In some embodiments,smartwatch 860 may include a variety of general-purpose computingrelated functions. For example, smartwatch 860 may provide access toemail, cellphone service, a user calendar, and so on. In variousembodiments, a health monitoring device may be a dedicated medicaldevice or otherwise include dedicated health related functionality. Forexample, a health monitoring device may monitor a user's vital signs,track proximity of a user to other users for the purpose ofepidemiological social distancing, contact tracing, providecommunication to an emergency service in the event of a health crisis,and so on. In various embodiments, the above-mentioned smartwatch may ormay not include some or any health monitoring related functions. Otherwearable devices are contemplated as well, such as devices worn aroundthe neck, devices that are implantable in the human body, glassesdesigned to provide an augmented and/or virtual reality experience, andso on.

System 800 may further be used as part of a cloud-based service(s) 870.For example, the previously mentioned devices, and/or other devices, mayaccess computing resources in the cloud (i.e., remotely located hardwareand/or software resources). Still further, system 800 may be utilized inone or more devices of a home other than those previously mentioned. Forexample, appliances within the home may monitor and detect conditionsthat warrant attention. For example, various devices within the home(e.g., a refrigerator, a cooling system, etc.) may monitor the status ofthe device and provide an alert to the homeowner (or, for example, arepair facility) should a particular event be detected. Alternatively, athermostat may monitor the temperature in the home and may automateadjustments to a heating/cooling system based on a history of responsesto various conditions by the homeowner. Also illustrated in FIG. 8 isthe application of system 800 to various modes of transportation. Forexample, system 800 may be used in the control and/or entertainmentsystems of aircraft, trains, buses, cars for hire, private automobiles,waterborne vessels from private boats to cruise liners, scooters (forrent or owned), and so on. In various cases, system 800 may be used toprovide automated guidance (e.g., self-driving vehicles), generalsystems control, and otherwise. These any many other embodiments arepossible and are contemplated. It is noted that the devices andapplications illustrated in FIG. 8 are illustrative only and are notintended to be limiting. Other devices are possible and arecontemplated.

It is noted that while the circuits discussed above have beenimplemented using NMOS and PMOS transistors, the disclosure is notintended to limit embodiments falling within its scope to these types ofdevices. Thus, in addition to various MOSFET types discussed above, thepresent disclosure also contemplates embodiments that use non-planardevices such as FinFETs, GAAFETs (Gate All Around FETs), among othertypes.

Embodiments implemented using Bipolar devices are also possible andcontemplated. The disclosure further contemplates that technologies thatare speculative as of this writing may be used to implement devices invarious embodiments of the circuits discussed herein. These technologiesinclude (but are not limited to) graphene transistors, carbon nanotubetransistors, gallium arsenide transistors, and so on. The use ofmemristors in certain circuit structures is also contemplated.

The present disclosure includes references to “an “embodiment” or groupsof “embodiments” (e.g., “some embodiments” or “various embodiments”).Embodiments are different implementations or instances of the disclosedconcepts. References to “an embodiment,” “one embodiment,” “a particularembodiment,” and the like do not necessarily refer to the sameembodiment. A large number of possible embodiments are contemplated,including those specifically disclosed, as well as modifications oralternatives that fall within the spirit or scope of the disclosure.

This disclosure may discuss potential advantages that may arise from thedisclosed embodiments. Not all implementations of these embodiments willnecessarily manifest any or all of the potential advantages. Whether anadvantage is realized for a particular implementation depends on manyfactors, some of which are outside the scope of this disclosure. Infact, there are a number of reasons why an implementation that fallswithin the scope of the claims might not exhibit some or all of anydisclosed advantages. For example, a particular implementation mightinclude other circuitry outside the scope of the disclosure that, inconjunction with one of the disclosed embodiments, negates or diminishesone or more the disclosed advantages. Furthermore, suboptimal designexecution of a particular implementation (e.g., implementationtechniques or tools) could also negate or diminish disclosed advantages.Even assuming a skilled implementation, realization of advantages maystill depend upon other factors such as the environmental circumstancesin which the implementation is deployed. For example, inputs supplied toa particular implementation may prevent one or more problems addressedin this disclosure from arising on a particular occasion, with theresult that the benefit of its solution may not be realized. Given theexistence of possible factors external to this disclosure, it isexpressly intended that any potential advantages described herein arenot to be construed as claim limitations that must be met to demonstrateinfringement. Rather, identification of such potential advantages isintended to illustrate the type(s) of improvement available to designershaving the benefit of this disclosure. That such advantages aredescribed permissively (e.g., stating that a particular advantage “mayarise”) is not intended to convey doubt about whether such advantagescan in fact be realized, but rather to recognize the technical realitythat realization of such advantages often depends on additional factors.

Unless stated otherwise, embodiments are non-limiting. That is, thedisclosed embodiments are not intended to limit the scope of claims thatare drafted based on this disclosure, even where only a single exampleis described with respect to a particular feature. The disclosedembodiments are intended to be illustrative rather than restrictive,absent any statements in the disclosure to the contrary. The applicationis thus intended to permit claims covering disclosed embodiments, aswell as such alternatives, modifications, and equivalents that would beapparent to a person skilled in the art having the benefit of thisdisclosure.

For example, features in this application may be combined in anysuitable manner. Accordingly, new claims may be formulated duringprosecution of this application (or an application claiming prioritythereto) to any such combination of features. In particular, withreference to the appended claims, features from dependent claims may becombined with those of other dependent claims where appropriate,including claims that depend from other independent claims. Similarly,features from respective independent claims may be combined whereappropriate.

Accordingly, while the appended dependent claims may be drafted suchthat each depends on a single other claim, additional dependencies arealso contemplated. Any combinations of features in the dependent claimsthat are consistent with this disclosure are contemplated and may beclaimed in this or another application. In short, combinations are notlimited to those specifically enumerated in the appended claims.

Where appropriate, it is also contemplated that claims drafted in oneformat or statutory type (e.g., apparatus) are intended to supportcorresponding claims of another format or statutory type (e.g., method).

Because this disclosure is a legal document, various terms and phrasesmay be subject to administrative and judicial interpretation. Publicnotice is hereby given that the following paragraphs, as well asdefinitions provided throughout the disclosure, are to be used indetermining how to interpret claims that are drafted based on thisdisclosure.

References to a singular form of an item (i.e., a noun or noun phrasepreceded by “a,” “an,” or “the”) are, unless context clearly dictatesotherwise, intended to mean “one or more.” Reference to “an item” in aclaim thus does not, without accompanying context, preclude additionalinstances of the item. A “plurality” of items refers to a set of two ormore of the items.

The word “may” is used herein in a permissive sense (i.e., having thepotential to, being able to) and not in a mandatory sense (i.e., must).

The terms “comprising” and “including,” and forms thereof, areopen-ended and mean “including, but not limited to.”

When the term “or” is used in this disclosure with respect to a list ofoptions, it will generally be understood to be used in the inclusivesense unless the context provides otherwise. Thus, a recitation of “x ory” is equivalent to “x or y, or both,” and thus covers 1) x but not y,2) y but not x, and 3) both x and y. On the other hand, a phrase such as“either x or y, but not both” makes clear that “or” is being used in theexclusive sense.

A recitation of “w, x, y, or z, or any combination thereof” or “at leastone of . . . w, x, y, and z” is intended to cover all possibilitiesinvolving a single element up to the total number of elements in theset. For example, given the set [w, x, y, z], these phrasings cover anysingle element of the set (e.g., w but not x, y, or z), any two elements(e.g., w and x, but not y or z), any three elements (e.g., w, x, and y,but not z), and all four elements. The phrase “at least one of . . . w,x, y, and z” thus refers to at least one element of the set [w, x, y,z], thereby covering all possible combinations in this list of elements.This phrase is not to be interpreted to require that there is at leastone instance of w, at least one instance of x, at least one instance ofy, and at least one instance of z.

Various “labels” may precede nouns or noun phrases in this disclosure.Unless context provides otherwise, different labels used for a feature(e.g., “first circuit,” “second circuit,” “particular circuit,” “givencircuit,” etc.) refer to different instances of the feature.Additionally, the labels “first,” “second,” and “third” when applied toa feature do not imply any type of ordering (e.g., spatial, temporal,logical, etc.), unless stated otherwise.

The phrase “based on” is used to describe one or more factors thataffect a determination. This term does not foreclose the possibilitythat additional factors may affect the determination. That is, adetermination may be solely based on specified factors or based on thespecified factors as well as other, unspecified factors. Consider thephrase “determine A based on B.” This phrase specifies that B is afactor that is used to determine A or that affects the determination ofA. This phrase does not foreclose that the determination of A may alsobe based on some other factor, such as C. This phrase is also intendedto cover an embodiment in which A is determined based solely on B. Asused herein, the phrase “based on” is synonymous with the phrase “basedat least in part on.”

The phrases “in response to” and “responsive to” describe one or morefactors that trigger an effect. This phrase does not foreclose thepossibility that additional factors may affect or otherwise trigger theeffect, either jointly with the specified factors or independent fromthe specified factors. That is, an effect may be solely in response tothose factors, or may be in response to the specified factors as well asother, unspecified factors. Consider the phrase “perform A in responseto B.” This phrase specifies that B is a factor that triggers theperformance of A, or that triggers a particular result for A. Thisphrase does not foreclose that performing A may also be in response tosome other factor, such as C. This phrase also does not foreclose thatperforming A may be jointly in response to B and C. This phrase is alsointended to cover an embodiment in which A is performed solely inresponse to B. As used herein, the phrase “responsive to” is synonymouswith the phrase “responsive at least in part to.” Similarly, the phrase“in response to” is synonymous with the phrase “at least in part inresponse to.”

Within this disclosure, different entities (which may variously bereferred to as “units,” “circuits,” other components, etc.) may bedescribed or claimed as “configured” to perform one or more tasks oroperations. This formulation—[entity] configured to [perform one or moretasks]—is used herein to refer to structure (i.e., something physical).More specifically, this formulation is used to indicate that thisstructure is arranged to perform the one or more tasks during operation.A structure can be said to be “configured to” perform some tasks even ifthe structure is not currently being operated. Thus, an entity describedor recited as being “configured to” perform some tasks refers tosomething physical, such as a device, circuit, a system having aprocessor unit and a memory storing program instructions executable toimplement the task, etc. This phrase is not used herein to refer tosomething intangible.

In some cases, various units/circuits/components may be described hereinas performing a set of tasks or operations. It is understood that thoseentities are “configured to” perform those tasks/operations, even if notspecifically noted.

The term “configured to” is not intended to mean “configurable to.” Anunprogrammed FPGA, for example, would not be considered to be“configured to” perform a particular function. This unprogrammed FPGAmay be “configurable to” perform that function, however. Afterappropriate programming, the FPGA may then be said to be “configured to”perform the particular function.

For purposes of United States patent applications based on thisdisclosure, reciting in a claim that a structure is “configured to”perform one or more tasks is expressly intended not to invoke 35 U.S.C.§ 112(f) for that claim element. Should Applicant wish to invoke Section112(f) during prosecution of a United States patent application based onthis disclosure, it will recite claim elements using the “means for”[performing a function] construct.

Different “circuits” may be described in this disclosure. These circuitsor “circuitry” constitute hardware that includes various types ofcircuit elements, such as combinatorial logic, clocked storage devices(e.g., flip-flops, registers, latches, etc.), finite state machines,memory (e.g., random-access memory, embedded dynamic random-accessmemory), programmable logic arrays, and so on. Circuitry may be customdesigned, or taken from standard libraries. In various implementations,circuitry can, as appropriate, include digital components, analogcomponents, or a combination of both. Certain types of circuits may becommonly referred to as “units” (e.g., a decode unit, an arithmeticlogic unit (ALU), functional unit, memory management unit (MMU), etc.).Such units also refer to circuits or circuitry.

The disclosed circuits/units/components and other elements illustratedin the drawings and described herein thus include hardware elements suchas those described in the preceding paragraph. In many instances, theinternal arrangement of hardware elements within a particular circuitmay be specified by describing the function of that circuit. Forexample, a particular “decode unit” may be described as performing thefunction of “processing an opcode of an instruction and routing thatinstruction to one or more of a plurality of functional units,” whichmeans that the decode unit is “configured to” perform this function.This specification of function is sufficient, to those skilled in thecomputer arts, to connote a set of possible structures for the circuit.

In various embodiments, as discussed in the preceding paragraph,circuits, units, and other elements may be defined by the functions oroperations that they are configured to implement. The arrangement andsuch circuits/units/components with respect to each other and the mannerin which they interact form a microarchitectural definition of thehardware that is ultimately manufactured in an integrated circuit orprogrammed into an FPGA to form a physical implementation of themicroarchitectural definition. Thus, the microarchitectural definitionis recognized by those of skill in the art as structure from which manyphysical implementations may be derived, all of which fall into thebroader structure described by the microarchitectural definition. Thatis, a skilled artisan presented with the microarchitectural definitionsupplied in accordance with this disclosure may, without undueexperimentation and with the application of ordinary skill, implementthe structure by coding the description of the circuits/units/componentsin a hardware description language (HDL) such as Verilog or VHDL. TheHDL description is often expressed in a fashion that may appear to befunctional. But to those of skill in the art in this field, this HDLdescription is the manner that is used to transform the structure of acircuit, unit, or component to the next level of implementationaldetail. Such an HDL description may take the form of behavioral code(which is typically not synthesizable), register transfer language (RTL)code (which, in contrast to behavioral code, is typicallysynthesizable), or structural code (e.g., a netlist specifying logicgates and their connectivity). The HDL description may subsequently besynthesized against a library of cells designed for a given integratedcircuit fabrication technology, and may be modified for timing, power,and other reasons to result in a final design database that istransmitted to a foundry to generate masks and ultimately produce theintegrated circuit. Some hardware circuits or portions thereof may alsobe custom-designed in a schematic editor and captured into theintegrated circuit design along with synthesized circuitry. Theintegrated circuits may include transistors and other circuit elements(e.g. passive elements such as capacitors, resistors, inductors, etc.)and interconnect between the transistors and circuit elements. Someembodiments may implement multiple integrated circuits coupled togetherto implement the hardware circuits, and/or discrete elements may be usedin some embodiments. Alternatively, the HDL design may be synthesized toa programmable logic array such as a field programmable gate array(FPGA) and may be implemented in the FPGA. This decoupling between thedesign of a group of circuits and the subsequent low-levelimplementation of these circuits commonly results in the scenario inwhich the circuit or logic designer never specifies a particular set ofstructures for the low-level implementation beyond a description of whatthe circuit is configured to do, as this process is performed at adifferent stage of the circuit implementation process.

The fact that many different low-level combinations of circuit elementsmay be used to implement the same specification of a circuit results ina large number of equivalent structures for that circuit. As noted,these low-level circuit implementations may vary according to changes inthe fabrication technology, the foundry selected to manufacture theintegrated circuit, the library of cells provided for a particularproject, etc. In many cases, the choices made by different design toolsor methodologies to produce these different implementations may bearbitrary.

Moreover, it is common for a single implementation of a particularfunctional specification of a circuit to include, for a givenembodiment, a large number of devices (e.g., millions of transistors).Accordingly, the sheer volume of this information makes it impracticalto provide a full recitation of the low-level structure used toimplement a single embodiment, let alone the vast array of equivalentpossible implementations. For this reason, the present disclosuredescribes structure of circuits using the functional shorthand commonlyemployed in the industry.

Numerous variations and modifications will become apparent to thoseskilled in the art once the above disclosure is fully appreciated. It isintended that the following claims be interpreted to embrace all suchvariations and modifications.

What is claimed is:
 1. An apparatus, comprising: an amplifier circuitconfigured to: receive one or more signals that encode a serial datastream that includes a plurality of data symbols; and perform acomparison of the one or more signals to a threshold value to generate arecovered data symbol; and a threshold circuit configured to: generate adelayed version of the one or more signals; generate a delayed datasymbol using the delayed version of the one or more signals; and adjustthe threshold value using the delayed data symbol.
 2. The apparatus ofclaim 1, wherein the threshold circuit includes: a delay circuitconfigured to apply hysteresis to the one or more signals to produce thedelayed data symbol; and a logic circuit configured to, for a currentlyreceived symbol, select the threshold value for the amplifier circuitbased on the delayed data symbol and an input code.
 3. The apparatus ofclaim 2, wherein the delay circuit includes a Schmitt trigger.
 4. Theapparatus of claim 2, wherein the input code is a static code providedfrom a control register.
 5. The apparatus of claim 2, wherein the inputcode is periodically updated based on a calibration.
 6. The apparatus ofclaim 1, further comprising an level shifter configured to transfer adata symbol received from the amplifier circuit from a first voltagedomain to a second voltage domain.
 7. The apparatus of claim 1, whereinthe threshold circuit is configured to change the threshold value from afirst level to a second level at a first delay time subsequent to atransition of a recovered data symbol from a first logic value to asecond logic value.
 8. The apparatus of claim 7, wherein the thresholdcircuit is configured to change the threshold value from the secondlevel to the first level at a second delay time subsequent to atransition of the recovered data symbol from the second logic value tothe first logic value.
 9. The apparatus of claim 8, wherein the secondlevel is greater than the first level.
 10. A method comprisingreceiving, by an amplifier circuit, one or more signals that encode aserial data stream that includes a plurality of data symbols;performing, using the amplifier circuit, a comparison of the one or moresignals to a threshold value to generate a recovered data symbol;generating, using a threshold circuit, a delayed version of the one ormore signals; generating, using the threshold circuit, a delayed datasymbol using the delayed version of the one or more signals; andadjusting, using the threshold circuit, the threshold value using thedelayed data symbol.
 11. The method of claim 10, wherein the thresholdcircuit includes a delay circuit and a logic circuit, and wherein themethod further comprises: producing the delayed data symbol, using thedelay circuit, wherein producing the delayed data symbol includes thedelay circuit providing hysteresis to the one or more signal; selectinga threshold value for a currently received data symbol using the logiccircuit based on the delayed data symbol and an input code.
 12. Themethod of claim 11, further comprising providing the input code, from aregister, to the logic circuit.
 13. The method of claim 11, furthercomprising performing a calibration to update the input code.
 14. Themethod of claim 10, further comprising the threshold circuit changingthe threshold value from a first level to a second level at a firstdelay time subsequent to a transition of a recovered data symbol from afirst logic value to a second logic value.
 15. The method of claim 14,further comprising the threshold circuit changing the threshold valuefrom the second level to the first level at a second delay timesubsequent to a transition of the recovered data symbol from the secondlogic value to the first logic value.
 16. A system comprising: atransmitter circuit configured to transmit one or more signals thatencode a serial data stream that includes a plurality of data symbols;and a receiver circuit configured to receive the one or more signals,wherein the receiver circuit includes: an amplifier configured tocompare voltage levels of the one or more signals to a threshold valueand to generate a recovered data symbol based on the comparisons; and athreshold circuit configured to generate, using a delayed version of theone or more signals, a delayed data symbol, and further configured toadjust the threshold value based on the delayed data symbol.
 17. Thesystem of claim 16, wherein the threshold circuit includes a Schmitttrigger configured to apply hysteresis to the one or more signals toproduce the delayed data symbol.
 18. The system of claim 17, wherein thethreshold circuit further includes a logic circuit configured to, for acurrently received symbol, select the threshold value for the amplifierbased on the delayed data symbol and an input code.
 19. The system ofclaim 18, wherein the system includes a calibration circuit configuredto periodically update the input code based on a calibration.
 20. Thesystem of claim 16, wherein the threshold circuit is configured tochange the threshold value from a first level to a second level at afirst delay time subsequent to a transition of a recovered data symbolfrom a first logic value to a second logic value, and further configuredto change the threshold value from the second level to the first levelat a second delay time subsequent to a transition of the recovered datasymbol from the second logic value to the first logic value.